High-speed processor-based systems have become commonplace in computing, communications, and consumer electronic applications to name a few. The processors in these high-speed systems, which are typically multi-gigahertz processors, continue to place higher demands on the associated subsystems. The transfer of information and signals required among the subsystems of these high-speed systems has led to increasing demands for integrated circuit interfaces that support the efficient high-speed transfer of information. Examples of such interfaces include the interfaces between processors and memory devices.
In chip-to-chip topologies, the time of flight of an electrical signal on an electrical interconnect can be an appreciably large portion of the overall bit-time, or period, of that electrical signal. In systems such as double data rate synchronous memory systems, a number of bits are treated as a collective group (i.e., referred to as a “byte”, for example 8 bits), and many bytes may be communicated in parallel between a memory controller and memory devices. Typically the data being transmitted between devices will be synchronous to some “transmit clock” that is common to each bit in the byte. Similarly, data sampling will be done using a “receive clock” that is typically common to each bit in the byte. However, due to the “per-byte clocking” nature of such systems, the maximum transfer rate capability of such a multi-byte interface will be limited by the pin-to-pin timing offsets created by variations in the time of flights of the individual electrical interconnects, as well as other factors. Consequently, there is a need for electronic circuits which provide the interface circuits of these interfaces with transmit and receive clocks that are optimized on a per-pin basis.